Bulk erase system for gas discharge display panels

ABSTRACT

In gaseous discharge display panels of the crossed conductor matrix type wherein the conductors are non-conductively coupled to the gas border discharge sites are normally maintained on for information or data display site conditioning purposes. According to the invention, rather than maintaining the border sites on while bulk erasing the entire panel, in the process of this invention, the border sites as well as the panel display areas are erased and then the border is rewritten. Circuitry is provided for inserting in the border conductors locating the border sites a voltage with the sustainer signal voltage following a bulk erase of all the signals due to sustainer control.

United States Patent 1 Wojcik [451 July 31,1973

[ BULK ERASE SYSTEM FOR GAs DISCHARGE DISPLAY PANELS [52] US. Cl....340/324 M, 315/169 R, 340/166 EL [51] Int. Cl. G081) 5/36 [58] Field ofSearch 340/324 R, 324 M, 340/166 R, 166 EL, 173 PL; 315/169 R, 169

TV; 313/108 B; 178/7.3 D

[56] References Cited UNITED STATES PATENTS 3,609,658 9/1971 Soltan340/166 R 3,644,925 2/1972 Kupsky 315/169 TV X 3,654,507 4/1972 Caras etal. 315/169 TV X 3,654,508 4/1972 Caras 315/169 TV X PrimaryExaminer-David L. Trafton Attorney-Donald Keith Wedding et al.

[57] ABSTRACT in gaseous discharge display panels of the crossedconductor matrix type wherein the conductors are nonconductively coupledto the gas border discharge sites are normally maintained on forinformation or data display site conditioning purposes. According to theinvention, rather than maintaining the border sites on while bulkerasing the entire panel; in the process of this invention, the bordersites as well as the panel display areas are erased and then the borderis rewritten. Circuitry is provided for inserting in the borderconductors locating the border sites a voltage with the sustainer signalvoltage following a bulk erase of all the signals due to sustainercontrol.

6 Claims, 7 Drawing Figures 60 K I S UINMRO ADDRESSING r-BI HALF HALF--b SELECT SELECT PUL-SER Pugs ELL r 5 TA NDARD 8 TA NDARD ADDRESS/N6ADDRESSING CIRCUITS (E VEN) CIRCUITS (E YEN) .506 T4 INER WRITE CON TROLd BORDER BULK E R455 2 SIGNAL SIGNAL BUS BUS llllllllllll S TANDARDADDRESSING CIRCUITS (W0) HALF SELECT PUL SEE.

r Jr

HALF SELECT PULSER PATENTEDJULB 1 I975 SHEET 1 [1F 2 7 G 64 sr (w I 836/ HALF sELEcT 2 2 PULSE/2 PULSE/2 IL r\ STANDARD STANDARD ADDRESS/N6ADDRESS/N6 A C/RCU/TS (EVEN) C/RCU/TS (EVEN) IIIIIIHIIH A A g'/ /20 "2la SUSTA/NER M a f If WR/TE CONTROL 4 A I I5 BORDER BULK ERASE \v .32SIGNAL SIGNAL BUS BUS 62 DA T4 8 CONTROL HHHHHH $774NDARD STANDARDADDRESSING ADDRESSING CIRCUITS (ODD) CIRCUITS (ODD) K54 HALF HALF SELECTSELECT PULSE/2 puLsE/z 63 E 74 Gr sx PNENTED 3, 750.159

SHEEI 2 UF 2 7'0 BORDER CONDUCTORS I 95 9/ r K mm M FIG. 2

ROW NORMAL F 8 WRITE r W, I NW L 1. W FIG. 3A sx ROW (14 COLUMN NORMALWRITE 1'1 B 1 lsov I {,NWM i I we FIG. 3B

- l sv COLUMN (14 I /N0R.MAL wm-rz AT I SELECTED SITE l 1 V y FIG. 3C sxsY NORMAL SUSTA/NED sx VSY) Hi F/G. a0

DATA AREA "V S/T'ES' OF PANEL d? TAT" CORNER.

: 501 052; :ITES 30, I, a3 ERASES BORDER\ TTE 2 HEP aw w, FIG. 35

BORDER AREA S/TES BULK ERASE SYSTEM FOR GAS DISCHARGE DISPLAY PANELS Thepresent invention is directed to a novel method and circuitry for bulkerasing a gaseous discharge display panel having inherent memory of thetype as disclosed in, for example, Baker et al. U.S. Pat. No. 3,499,167.

As disclosed in the above-mentioned Baker et al. patent, there are anumber of ways for conditioning the discrete information displaydischarge sites in such panels for operating at substantially uniformpotentials. In a preferred case and one that is currently being used,photon conditioning as is described in the Baker et al. patent, anentire row or column of the sites on the border are maintained in afired or on condition during normal operation of the panel with thelight produced being masked or blocked off from the normal viewing areaor otherwise not used for display purposes. In the past, these bordersites were turned on and supplied with sustainer potential from the samesustainer sources as the normal viewing or display area of the panel.Thus, when it was desired to erase a page of data or information thatwas being displayed in the viewing area of the panel, simultaneously, bycontrol of the sustainer voltages, the border sites were also erased.This is called bulk erase" and as used herein means the turning off ofall the information or data display sites on the panel while the borderis turned on at the end ofthe erase cycle for conditioning of thesesites for discharge an entry of new information to the panel. IN thepast, effort has been made to avoid halfselection pulses. In accordancewith this invention, while the border sites which are to be maintainedon for conditioning purposes, are driven from the same sustainer, thecircuitry according to the present invention operates by inserting avoltage in series with the sustainer signal voltage to the borderconductions, following a bulk erase of all sites and panels due tosustainer control. This signal may be used to initially fire the panelon startup and fired periodically in case of a power failure ortransient. Corner border sites therefor see as their applied voltagesthe sustainer and each of the half select voltages on the borderconductors and this magnitude of voltage is sufficient to assurereliable turn on of at least the corner border sites.

The method and circuitry of the present invention provides a simplifiedbulk erase process and is a simplification from circuitry standpoint andprovides certain characteristics and flexiblity to the system at noadditional expense.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects,advantages and feature of the invention will become more apparent inlight of the following specification taken in conjunction with theaccompanying drawings wherein:

FIG. I is a stylized block diagram of the circuitry in accordance withthe invention with a isometric showing of a gas discharge panel to whichthe invention has been applied (several circuitry blocks beingduplicated for clarity of illustration only), FIG. 2 is one schematicdrawing of the half select pulsers" for the purposes of adding a halfselect voltage pulse onto the sustainer to the border sites on thepanel, and

FIG. 3 (A, B, C, B and E) are wave form diagrams which are provided tosupply explanation of the operation of the invention.

Referring now to FIG. 1, gaseous discharge display panel 10 ispreferably of the type disclosed in Baker et al. U.S. Pat. No. 3,499,]67, filled with a neon-argon gas mixture (99.9% neon and 0.1% argon) asis disclosed in Nolan application Ser. No. 764,577 filed Oct. 2, 1968,and as further modified by a dielectric or insulating overcoating (notshown) on the dielectric coatings of the aforementioned Baker et al.patent of a lead oxide. Typically, the discharge gap distance in suchpanels selected to be between 4 and 6 mils. The panel 10 is constitutedby a row conductor plate 11 and a column conductor plate 12 joined inspaced apart relation by a spacer sealant (not shown) so as to providethe aforementioned discharge gap distances and a thin gas dischargechamber.

The row conductor plate 11 carries a row conductor array 13 in thewriting or data display area V and a row border array 14 and 15 at thesides thereof. The column conductor plate 12 is identical, having a column conductor array 16 in the writing or viewing area of data displayarea V" and border or side conductors l7 and 18 respectively. Alternateones of the conductors in array 13 are grouped and extended towards theopposite ends 20 and 21 of panel 12 and in a similar .fashion, alternateones of the conductors in array 16 are extended to the opposite ends 22and 23 respec tively, of column conductor plate 12. in like manner,alternate ones of the border conductors are extended to the edges oftheir respective plates and adapted for connection to supply potentials.It will be appreciated that instead of extending the conductors of anarray to opposite edges they may all be extended towards the same edgeand receive operating potentials from the same side or edge. Thus,instead of extending the row conductors (writing conductors l3 andborder conductors 14 and 15) towards the edge 22, these may all beextended towards edge 23 of row plate 12 and be served with operatingpotentials from the same side or edge. in like manner, the conductors oncolumn plate 12 may be arranged and energized in the same fashion. Thus,the illustration in FIG. 1 of separate circuitry for addressing for thesustainer voltages and the border half select pulsers is for the purposeof illustration only, it being understood that they may be, andpreferably are, driven from the same supply. Since the border or sideconductors in an array will be supplied with the same potential, allthose on one side may be connected together. Thus, if there are severalconductors constituting border conductors 17, for example, they may beconnected together at their ends in the forming of these conductors.

The viewing area of the panel is labeled V" in FIG. 1, and the borderareas are labeled 8". In a rectangularly shaped panel there will be fourborder areas. The border conductors in each array while crossing eachother in the corners (as at 30, 31, 32 and 33) are normally lit alongthe entire border areas B1, B2, B3 and B4 to provide sufficient photonconditioning for the entire data display or viewing area V" of thepanel. It will be appreciated therefore that each of the borderconductors in the areas B1, B2, B3, B4 which cross a row conductor 13 ora column conductor 16, respectively (and extend into and across theviewing area V to form the light emitting display matrix), willcooperate with the border conductors to provide the necessary operatingpotentials to the border sites in the border areas B1, B2, B3 and B4.However, the half select pulsers to be described later herein are onlyapplied to the border conductors in conjunction with the sustainerpotentials so as to write the border conductors only. (The term write"means the initiation of a sequence of discharges at selected sites, andthe term erase" means the termination of a discharge; and, the termdischarge" means the momentary or pulsing discharge nature of the sitesas described in said Baker et al. patent). The half select voltages" arenot applied to the row and column conductors because such voltages wouldtend to turn on all of the sites along the conductor to which they areapplied, which, however, satisfies the objective of turning on theborder sites.

The panel 10, per se, as well as the sustainer genera tors andaddressing circuits is conventional insofar as this invention isconcerned. The row conductor array 13 is supplied with dischargecondition manipulating pulse potentials from standard addressingcircuits 60 and 61 which receive information and control signals from adata and control source 62. The sustainer sources have a common groundor reference point 8 so the addressing circuits 60 and 61 float uponsustainer potentials from row sustainer generator sources 63 and 64,respectively. The addressing circuits 60 and 61 may be of the typedisclosed in D. L. Leuck application Ser. No. 135,621 filed Apr. [9,l97l and the sustainer generators may be of the type disclosed in D. S.Wojcik application Ser. No. l35,022 filed Apr. 19, I971. In a similarmanner, the column conductors in array 16 are driven by addressingcircuits 70 and 71 which float on column sustainer generators 73 and 74.

THE PRESENT INVENTION As described above, the border sites in cornerareas 30 and 31, 32 and 33 and border areas B1, B2, B3, B4 are driven orsupplied by sustainer potential from sources 63, 64 for the border rowconductors l4 and and 73, 74 for the border column conductors 17 and 18.It is possible to turn off a site and remove information at randominformation sites in the panel by applying an erase pulse to selectedconductors crossing each other at the site and thereby selectivelyremove information from the panel at any selected discrete site.However, it frequently is an advantage to erase the entire panel, whichmeans to eliminate the memory or wall voltage due to stored charges atall information display sites in the panel. In the bulk erase processdescribed herein, this is done by modifying the sustainer potential asapplied to all the sites for one or more cycles or periods and thenreapplying the sustainer potential in the normal fashion. As shown inFIG. 3(D) bulk erase is achieved by simply narrowing the width of thesustainer for at least one half cycle. Thus, when the sustainer voltagepulses are normally 150 volts and 5 microseconds in width (and at 3050kHz) the erase pulse E can be the same magnitude and rate sustainer buthaving a 2 microsecond width. The normal sustainer voltage applied tothe gas at a site shown in FIG. 3(C), is constituted by the sustainervoltages applied to the row and column conductor arrays as illustratedin FIG. 3(A) and FIG. 3(8).

The mechanism of discharge at substantially uniform potential requires,among other things, the existence or presence of some charged particlesat each discrete discharge site, which implies some conditioningprocesses These conditioning processes have involved, in the past, theuse of radiation by ultraviolet energy on the panel, use of radioactivesources in the panel, conditioning pulse voltages applied to theconductor arrays and, as in the aforementioned Baker et al. U.S. Pat.No. 3,499,167, the elimination of the discharge isolation structurespermits photon conditioning of the sites by turning on the border sitesand maintaining the border sites on during the addressing of selectedsites in the viewing or writing area of the panel.

In the past it was sought to maintain the border sites on while erasingthe whole information or data display of the panel. According to thepresent invention, simultaneously wtih the bulk erasing of the data fromthe entire panel, the border sites are also erased and then the bordersites are immediately rewritten by application of the normal sustainerpotential along with a border write signal potential. Moreover, thisborder write signal potential (B is applied to only the borderconductors of the conductor arrays and, when algebraically added to thesustainer potential on the border conductors, is of sufficient magnitudeto initiate the discharges at the border sites without a correspondingpulse on the opposite conductor in the areas B1, B2, B3, B4. Thus, onbulk erase, the sustainer voltages V from sources 63 and 64 arecontrolled by data and control source 62 to cause a relatively shorttime duration (about 2 microsecond duration as compared to a normalsustainer of about 5 microsecond duration) voltage pulse Ep to besubstituted in place of the normal sustainer pulse at the selected timeinterval or period. In FIG. 3A a normal write pulse N row as applied toa selected row conductor is approximately one-fourth the voltage neededto initiate a discharge. A further one-fourth is simultaneously suppliedby a normal write pulse N col. (FIG. 3(B)) is applied to a columnconductor locating the selected site in data viewing or display area V.The sum of these two voltages with the sustainer voltage at the selectedsite (FIG. 3(C)) is sufficient to turn on any selected site. It will benoted that the memory or wall voltage of the panel will maintain thesites in an on state. However, since any voltage applied to a conductorof an array is also applied to all other discharge sites located by thatconductor, the voltage applied thereto cannot be of a magnitude to turnon unselected sites. However, in the case of the border sites, theobjective is to turn on all sites and hence the voltage applied to theborder conductors must be of a magnitude which, when added to thesustainer, will turn on the sites in border area B1, B2, B3 and B4without adversely affecting the sites in the data display or viewingareas V of the panel.

A simplified circuit for use as a border site writer is shown in FIG. 2.The circuit includes transistor 01 which is biased on or conductive by avoltage from a source such as battery and controlled or turned off by acontrol signal from data and control circuit 62 applied via transformerT1 and resistor-capacitor coupling circuit 91. With transistor Q1 beingnormally conductive, the sustainer voltage V (which may be for the rowor column conductor arrays) appears at the output terminal 92. A second,normally non-conductive, transistor switch 02 has its collector-emitterconnected in series with a volt source, such as battery 93, and couplingresistor 94 and in shunt with the collector emitter circuit oftransistor Q1. Transistor O2 is controlled by a signal coupled from dataand control circuit 62 by way of transformer T2 and shunt resistor 95.When transistor 01 is rendered non-conductive or a high impedance,transistor O2 is rendered conductive so that the 150 volt source 93 isadded to the sustainer voltage as a short pulse B This action occurssimultaneously at all half select pulsers 80, 81, 83, 84 so that theborder write pulses E and B (FIGS. 3A, 3B and 3E) are applied to theborder conductors (14-15 and 17-18) in each array. As shown in FIG. 3Ethe corner border sites 30, 31,32 and 33 will have a much largeramplitude voltage applied thereto so that the initial discharges atthese sites can be more reliably initiated.

Shunt diode D1 is a bypass for sustainer displacement currents asdisclosed in the aforementioned Leuck patent application and Johnsonapplication Ser. No. 60,402 filed Aug. 5, 1970.

It will be noted that in the areas B1, B2, B3, E4, the normal writingcircuits 60, 61, 70, 71 are not energized during the writing of theborder sites in those areas. Thus, as discussed above, the rowconductors in the areas B1 only are provided with the half select pulseswhich cooperate with the sustainer voltages applied via the standardaddressing circuits. However, in the border areas 30, 31, 32 and 33 thesustainer voltage coacts with the sustainer voltages and the half selectpulser circuits.

It will be appreciated that various modifications and changes obvious tothose skilled in the art maybe incorporated in the practice of thisinvention without departing from the spirit or scope of the claimsappended hereto.

What is claimed is:

l. A method of operating a gas discharge data display panel of the typehaving a dielectrically coated rowconductor array on a first supportplate. a dielectrically coated column conductor array on a secondsupport plate, means joining said plates in spaced apart relation with agaseous discharge medium between said dielectrically coated conductorarrays, a selected number of conductors in each said array locatingborder discharge sites which are used as non-data display areas, andwherein the operating potentials to said conductor arrays includes aperiodic voltage for sustaining discharges once initiated, said periodicsustainer voltage being of a magnitude insufficient to initiate adischarge at any site but of sufficient magnitude to maintain dischargesonce initiated at any site, and a data entering discharge initiatingsignal voltage for algebraic addition to said sustainer voltagepotential, said method including the step of bulk erasing data displayedon said panel by modifying sustainer voltages from conductors of atleast one of said arrays,

the improvement comprising.

simultaneously with the bulk erasing of data from the entire panel,erasing said border sites and then rewriting said border sites byapplication of said sustainer voltage thereto along with a border writesignal voltage.

2. The invention defined in claim 1 wherein said border write signalvoltage for said border conductors is applied to at least one of saidconductor arrays and, when algebraically added to said sustainerpotential on said border conductor, is ofsul'ficient magnitude toinitiate discharges at said border sites.

3. The invention defined in claim 2 wherein said border write signalvoltage is applied to all said border conductors in each array so thatthe corner border sites are turned on by a voltage comprised of thealgebraic sum of said sustainer voltage and twice the magnitude of saidborder write signal voltage.

4. In a gaseous discharge display panel having rowcolumn conductorarrays, non-conductively coupled to a gas discharge medium in thechamber space between said row and said column conductor array and aborder conductor array cooperating with the ends of the conductors inthe row-column conductor arrays which, for the purpose of photonconditioning of information display sites in the panel, are on duringthe entry of information to be displayed on said panel, the improvementin the bulk erasing of said panel which comprises,

means for modifying the sustainer voltage on at least one of said arraysfor at least one period thereof, and

means for turning said border sites on prior to the entry of informationto said panel.

5. The invention defined in claim 4 wherein said means for turning onsaid border sites prior to entry of new information to said panelincludes a source of border pulse potential selectively connectable onlyto at least one of said border conductors which, border pulse potentialalgebraically added to the sustainer voltage to said at least one borderconductor is sufficient to cause a discharge at any border site only onthe panel located by said at least one border conductor.

6. The invention defined in claim 4 wherein the border conductors ineach array are supplied with said border pulse potential so that thecorner border sites have applied thereto said sustainer potential andalgebraically added thereto twice the magnitude of said border pulsepotential.

l I! t! I I

1. A method of operating a gas discharge data display panel of the typehaving a dielectrically coated row-conductor array on a first supportplate, a dielectrically coated column conductor array on a secondsupport plate, means joining said plates in spaced apart relation with agaseous discharge medium between said dielectrically coated conductorarrays, a selected number of conductors in each said array locatingborder discharge sites which are used as non-data display areas, andwherein the operating potentials to said conductor arrays includes aperiodic voltage for sustaining discharges once initiated, said periodicsustainer voltage being of a magnitude insufficient to initiate adischarge at any site but of sufficient magnitude to maintain dischargesonce initiated at any site, and a data entering discharge initiatingsignal voltage for algebraic addition to said sustainer voltagepotential, said method including the step of bulk erasing data displayedon said panel by modifying sustainer voltages from conductors of atleast one of said arrays, the improvement comprising, simultaneouslywith the bulk erasing of data from the entire panel, erasing said bordersites and then rewriting said border sites by application of saidsustainer voltage thereto along with a border write signal voltage. 2.The invention defined in claim 1 wherein said border write signalvoltage for said border conductors is applied to at least one of saidconductor arrays and, when algebraically added to said sustainerpotential on said border conductor, is of sufficient magnitude toinitiate discharges at said border sites.
 3. The invention defined inclaim 2 wherein said border write signal voltage is applied to all saidborder conductors in each array so that the corner border sites areturned on by a voltage comprised of the algebraic sum of said sustainervoltage and twice the magnitude of said border write signal voltage. 4.In a gaseous discharge display panel having row-column conductor arrays,non-conductively coupled to a gas discharge medium in the chamber spacebetween said row and said column conductor array and a border conductorarray cooperating with the ends of the conductors in the row-columnconductor arrays which, for the purpose of photon conditioning ofinformation display sites in the panel, are on during the entry ofinformation to be displayed on said panel, the improvement in the bulkerasing of said panel which comprises, means for modifying the sustainervoltage on at least one of said arrays for at least one period thereof,and means for turning said border sites on prior to the entry ofinformation to said panel.
 5. The invention defined in claim 4 whereinsaid means for turning on said border sites prior to entry of newinformation to said panel includes a source of border pulse potentialselectively connectable only to at least one of said border conductorswhich, border pulse potential algebraically added to the sustainervoltage to said at least one border conductor is sufficient to cause adischarge at any border site only on the panel located by said at leastone border conductor.
 6. The invention defined in claim 4 wherein theborder conductors in each array are supplied with said border pulsepotential so that the corner border sites have applied thereto saidsustainer potential and algebraically added thereto twice the magnitudeof said border pulse potential.